The present invention relates in general to manufacture of semiconductor devices, and in particular to various techniques to manufacture semiconductor devices having significantly larger size and circuit density.
With advances in design and manufacture of semiconductor devices, it has become possible to integrate increasingly larger amounts of circuitry on a single die. Today the size of a die can easily approach the limits of existing manufacturing equipment. Semiconductor manufacturing equipment that are designed to process silicon wafers divide each wafer into various reticles that are processed simultaneously. For a relatively smaller die, a reticle may contain multiple dies. However, it is now possible to design and integrated enough circuitry on a die that may be as large or even larger than a reticle. There is therefore a need for solutions to the problems posed by die sizes reaching the to reticle limitations of semiconductor manufacturing equipment.
The present invention provides various techniques that allow for designing and manufacturing integrated circuits that consume silicon area larger than a single reticle. The invention develops novel stitching techniques that permit communication across reticles. Various techniques to ensure continuity of interconnections and sealing mechanisms across the stitch region are also disclosed. The stitch extended device is readily scalable to allow quick transitions to next generation technologies.
Accordingly, in one embodiment, the present invention provides an electronic device including a first semiconductor die having first logic circuitry coupled to a first plurality of interconnect lines, and further having a first buffer coupled to a one of the first plurality of interconnect lines; and a second semiconductor die having second logic circuitry coupled to a second plurality of interconnect lines, and further having a second buffer coupled to one of the second plurality of interconnect lines, wherein, the first buffer couples to the second buffer across a stitch region between the first and second semiconductor dies.
In another embodiment, the present invention provides a programmable logic circuit including a plurality of logic elements coupled to a plurality of interconnect lines; and a plurality of bi-directional buffers respectively coupled to the plurality of interconnect lines, wherein, the plurality of bi-directional buffers are configured to couple the plurality of interconnect lines to a second plurality of interconnect lines of a programmable logic circuit on an adjoining die.
In yet another embodiment, the present invention provides a method of manufacturing an electronic device that includes the steps of fabricating first logic circuitry having a first plurality of interconnect lines on a first die on a silicon wafer; fabricating second logic circuitry having a second plurality of interconnect lines on a second die on said silicon wafer adjacent to the first die; and providing a plurality of bi-directional buffers to selectively couple the first plurality of interconnect lines on the first die to the second plurality of interconnect lines on the second die over a stitch region between the first and second die via a plurality of stitch interconnect lines.
The present invention also provides for a method of manufacturing an electronic device that includes the steps of fabricating an integrated circuit using a first generation technology on at least two silicon dies stitched together by bi-directional interconnect lines; shrinking the size of the integrated circuit by multiplying it by a second generation technology scale factor to arrive at a scaled down integrated circuit; and fabricating the scaled down integrated circuit using said second generation technology on a single die.
A better understanding of the nature and advantages of the reticle stitching techniques of the present invention may be gained by reference to the detailed description and drawings below.